Re: For digital designers, Can u tell me which tool is that?
hey ahmad
i'm sorry in being late to reply
well, i can give u only some info
i'm just into some of these tools
for designcompiler, it's a synthesizer, that uses the specs and constraints of the design to produce a netlist circuit with optimizations such as for area or timing for instance...it's like leonardo spectrum of mentor
primetime, it's for static timing analysis, so it deals with timing issues such as setup and hold time violation, min pulse width, clock skew, etc.
power complier is for the analysis and optimization of average power consumption at the RTL level and gate level
VCS is for RTL verification
tetramax is for ATPG (automatic test pattern generation)
formality is for equivalence checking
from Cadence, SoC Encounter is for place and route
Virtuoso is for layout
for magma, there is blast RTL for synthesis and blast fusion for place and route
i hope that was useful
regards,
Salma