For a Xilinx Spartan 3E design - I need an asymmetric Fifo

[BenKropp]

Asymmetric Fifo

Hi,
for a Xilinx Spartan 3E design I need an asymmetric (24Bit and 16Bit Port), asynchronous Fifo.
I tried to build it using the Xilinx LogiCore generator but it seems that this combination isn't possible.
Any suggestions?

 

[tariq786]

Asymmetric Fifo

You should download the book
"FPGA prototyping by verilog example by Pong P. Chou"

available on rapidshare or google it

Read section 4.5.3 in chapter 4

 

[nareshgtr]

Re: Asymmetric Fifo

Hi BenKropp,
You can generate 24bit and 16 bit port asynchronous fifos using coregen in xilinx. Which version of Xilinx you are using. Still if you want write the code for asyncfifo i am attaching two pdfs. By reading those you can design async fifos with any width and any depth.
Regards
V. Naresh Kumar

 

[BenKropp]

Re: Asymmetric Fifo

thx for your help, but I'm looking for a fifo providing a 24 Bit write port and 16 Bit read port and different write and read clocks.
I'm using ISE9.2i and did not find a way to generate this port ratio with coregen.
nareshgtr, maybe I overlooked something?

 

[j_andr]

Re: Asymmetric Fifo

I'm looking for a fifo providing a 24 Bit write port and 16 Bit read port/.../

the easiest solution is to generate with the coregen 32/16 fifo which as far as
I know is available in ise and just use 24 'input' bits out of the 32;
a little, but not much, complicated way is to use 24/24 fifo
and write your own logic which assigns data from fifo to 16 bit vector
in a desired way;
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