This is because of different current source and sink capabilities.
Let's assume NMOS input pair
1)Current sink for differential pair is Iss
2)Current source for both differential pair and cascode branch is I1
3)Current sink for cascode branch is I2
Normally we set I1=I2+0.5*Iss
If all Iss flows through one input NMOS, another one will be turned off
then SR-=I2-max{(I1-Iss), 0}
and SR+=I1-I2
I think slewing phenomena is much more complex than that describes in razavi. It may caused by first stage and second stage later, and miller effect will slow down the slewing in second stage.
Problem with with small output stage current (I0) is when one part of the output stage has no current during the slewing, and you need more time for recovery from off state. This problem could be solved setting slightly higher (1.5*I0) current of the output stage but then dc gain drops (because of ro~1/I).