module top
(
input wire clk
,input wire async_rst_n
,input wire in
,output wire out
);
wire sync_rst_n;
// reset synchronizer
resetsync i0
(
.iClk (clk ),
.async_rst_n (async_rst_n ),
.sync_rst_n (sync_rst_n )
);
// dut uses sync_rst_n asyncrounousely
dut i1
(
.clk (clk ),
.rst_n (sync_rst_n),
.d_in (in ),
.d_out (out )
);
endmodule
module resetsync
(
input wire iClk
,input wire async_rst_n
,output reg sync_rst_n
);
reg rst_n_meta;
always @ (posedge iClk or negedge async_rst_n)
begin
if (~async_rst_n)
begin
rst_n_meta <= {1'b0};
sync_rst_n <= {1'b0};
end
else
begin
rst_n_meta <= 1'b1;
sync_rst_n <= rst_n_meta;
end
end
endmodule
module dut
(
input wire clk
,input wire rst_n // asynchronous active low reset
,input wire d_in
,output reg d_out
);
// d-ff with asynchronous rest
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
d_out <= 1'b0;
else
d_out <= d_in;
end
endmodule