Flop and Latch based Design

[pintuinvlsi]

Hi,
I want to know the difference between the Lacth based and flop based design. What are the difference between these two and which one is better.
How we can take care of this in design.
If any one can tell with some examples, it would be great.
If some time has some good material, please give a pointer to that.

Thanks in advance,

 

[WzWzWz]

flop based design is populor and most EDA tools supported. Latch based design may be better in low power and area, but is difficult in many other fields.

 

[cafukarfoo]

Latch based design is not good for DFT purpose.

During scan insertion, the flop will be change to scan flop.

 

[rsrinivas]

i have seen that high speed designs are latch based....
is it true...?
may be yes as it requires half the amount of flops...

 

[waynejwd]

Flop based design always uses HDL coding and synthesis.
Latch based design always uses 2 sets of clock with different phase. And 2 latches are clocked by these 2 clocks in sequential. These kind of design often draws the circuit in Virtuso, analog cricuit design tools in Cadance, and then export the netlist, which is used to do simulation and P&R.

 

[alok_msh]

Latch Based Design can be handled these days by the DFT Tools by using LSSD (I think Level Sensitive Scan Design. It is certainly difficult then a MuxD Scan Design though.

 

[pintuinvlsi]

Can anyone tell Whether Latch based design has also timing parameters like set up or hold, or we don't check for these parameters?

@WzWzWz
Can you give some more hint how latch based design takes less power and area?

 

[phoenixfeng]

latch based design also has timing parameters, and they should be checked as Flip-Flop based design