Jul 17, 2017 #1 A a2vlsi Newbie level 3 Joined Jul 17, 2017 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 24 If my signal coming into ON domain is floating (not isolate by isolator), then what probable issue seems to be as per low power concept.
If my signal coming into ON domain is floating (not isolate by isolator), then what probable issue seems to be as per low power concept.
Jul 18, 2017 #2 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,568 Helped 397 Reputation 794 Reaction score 467 Trophy points 1,363 Activity points 14,883 Without fully understanding what you are doing, I would assume the signal will eventually be routed to a CMOS gate. So you will have a transistor with a floating input gate. It will not work reliably.
Without fully understanding what you are doing, I would assume the signal will eventually be routed to a CMOS gate. So you will have a transistor with a floating input gate. It will not work reliably.
Jul 19, 2017 #3 H hyun5226 Newbie level 5 Joined Jul 18, 2013 Messages 8 Helped 2 Reputation 4 Reaction score 2 Trophy points 3 Activity points 41 If you mentioned, I think leakage power will occur on the floating gate (in ON domain). On floating gate, Because It is possible to propagate X signal (neither 0 nor 1), leakage will occur.
If you mentioned, I think leakage power will occur on the floating gate (in ON domain). On floating gate, Because It is possible to propagate X signal (neither 0 nor 1), leakage will occur.
Jul 19, 2017 #4 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,568 Helped 397 Reputation 794 Reaction score 467 Trophy points 1,363 Activity points 14,883 hyun5226 said: If you mentioned, I think leakage power will occur on the floating gate (in ON domain). On floating gate, Because It is possible to propagate X signal (neither 0 nor 1), leakage will occur. Click to expand... leakage is the least of your concerns. the design will not work.
hyun5226 said: If you mentioned, I think leakage power will occur on the floating gate (in ON domain). On floating gate, Because It is possible to propagate X signal (neither 0 nor 1), leakage will occur. Click to expand... leakage is the least of your concerns. the design will not work.
Jul 19, 2017 #5 A a2vlsi Newbie level 3 Joined Jul 17, 2017 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 24 ThisIsNotSam said: leakage is the least of your concerns. the design will not work. Click to expand... During synthesis we always have floating signal and design will work. crowbar or shot circuit current is the perfect concern. Please correct me, if I am wrong.
ThisIsNotSam said: leakage is the least of your concerns. the design will not work. Click to expand... During synthesis we always have floating signal and design will work. crowbar or shot circuit current is the perfect concern. Please correct me, if I am wrong.
Jul 19, 2017 #6 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,568 Helped 397 Reputation 794 Reaction score 467 Trophy points 1,363 Activity points 14,883 a2vlsi said: During synthesis we always have floating signal and design will work. crowbar or shot circuit current is the perfect concern. Please correct me, if I am wrong. Click to expand... You are very wrong. Simulate a CMOS inverter. Let the input gate floating. See what you get. Synthesis is about design manipulation. It cares very little if signals are connected or to where. The actual silicon would not work, 100% guaranteed.
a2vlsi said: During synthesis we always have floating signal and design will work. crowbar or shot circuit current is the perfect concern. Please correct me, if I am wrong. Click to expand... You are very wrong. Simulate a CMOS inverter. Let the input gate floating. See what you get. Synthesis is about design manipulation. It cares very little if signals are connected or to where. The actual silicon would not work, 100% guaranteed.