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[SOLVED] Floating pins of a DDR3 memory

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rahdirs

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Hi,

I am using a DDR3 which has 32 pins for data bus,in my design i'm only using a 24 bit data bus.The remaining 8 pins will be left as floating.

I can't connect the pins on the board to GND now,is the only option left to me now is to drive them to '0' from fpga ?
I know it is not recommended to have floating pins but will it have any affect ?
 

AMS012

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You can leave the pins you are not using floating. It will not cause any harm.
 

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The pins are DQ pins, they are both inputs and outputs depending on if you are writing or reading respectively. So you can't just drive a 0 out of the FPGA constantly.

If you never plan on using those pins (ever) then you could ground them through some 10K resistors, so they aren't floating. But if there is ever a chance the 8-bits might get used in the future (enhancement, new requirement, etc), then I would probably make my DDR3 core 32-bits and ground the user write interface going out and not connect the read interface to those bits. Then if you ever need to add them back in the logic will be available to use, also the tools will strip out the user interface logic but leave the I/O drivers as it will still control the read/write input/output control.
 

rahdirs

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The pins are DQ pins, they are both inputs and outputs depending on if you are writing or reading respectively. So you can't just drive a 0 out of the FPGA constantly.

I'm not using those extra DQ pins & will most probably not use them.While generating constraints,there was a warning given by Xilinx tool that the extra 8 pins are not taken care in the XDC.

Grounding the pins via a 10 k resistor is not possible now,so i was asking if i should just drive them to '0'
 

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So they are connected to the FPGA?

Then do the other thing I suggested, drive the write side of the IP core's user I/F to 00000000 and don't use the read side (keep all the xdc constraints though). You might get a warning from the tools, but just ignore it (add it to the ignore list).
 
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    rahdirs

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rahdirs

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So they are connected to the FPGA?

Then do the other thing I suggested, drive the write side of the IP core's user I/F to 00000000 and don't use the read side (keep all the xdc constraints though). You might get a warning from the tools, but just ignore it (add it to the ignore list).
Yes they are connected to fpga.
That is what i meant by driving '0' from fpga.The 24 DQ bits which i'm using for read/write will be inout but the remaining 8 bits will only be 8 OUT bits.
In XDC if i constraint them to their pins to which they are physically connected on fpga,i don't think the tool would throw up a warning.

As of now,i am not driving those 8 pins to '0',do you think there could be any problem while reading the written data etc.. ?
 
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Micron DDR3 datasheets have a suggestion how to connect unused pins.

It says, use 1k pullup/pulldown resistors to set DQS pairs to inactive level, also pulldown DM to inactive. DQ pins might be pulled up or down by 1k or left floating.
 

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