Got it. You dont see any issue in RTL simulations , where as netlist simulations are having X.
Can you check these things?.
1. Is timing closed for this block.
2. check the timing reports for the corners , you are running simulations and make sure you dont have any Setup and hold violations.
3. Are you running the same clock frequency, where STA is closed?.
4. To make sure, timing is not a problem, run the netlist simulations with 1Mhz.
5. Do you see any SDF related errors/warnings in the log report. Is there any annotation issues?.
Regards,
Sam