Reviewing the discussion, I found that it's mixing unrelated problems, e. g. behavior of FF as such, behaviour of FPGA and simulation. Your adding the topic of different supply voltage rise.
- A FF in general, also a counter, e. g. as a TTL or CMOS logic device, usually has no power-on-reset (POR). In most cases, it has an accidental initial state. A POR should be designed in the circuit, preferably in a way that's unsensitive to slow and non-monotonic supply voltage rise and such issues.
A FF in a CPLD or FPGA mostly has a POR respectivly a defined power-on state.
In simulation, an unknown state is assumed for all registers usually. Thus an additional initialisation of registers for simulation may be necessary to make the design work at all, even for a simple /2 clock divider.