Seal ring is a judgment call, an environmental reliability
thing (mobile ion ingress). I would always put one but
perhaps your next level assembly has all that under
control (or maybe they only believe so). Get it in writing.
Pad placement comes from the options for assembly,
whether this is direct to PCB, or for a fired substrate,
or some other scheme; copper pillar vs solder pillar vs
solder ball vs hollow ball all have their own "sweet
spot" and wrung-out assembly flows / rules. Look to
the customer or service provider for this. Same for
UBM / plating rules.
Corner cells may be about die singulation / inspect
yield, or it may be that these are where primary
ESD clamps are housed. We don't know. You should
find out what you'd be eliminating and what impact
using (say) a more aggressive smaller corner cell
might have, based on your die processing vendor's
reject rate for passivation chip-off particularly.
You should put at least rudimentary ESD protection
on all pads (possibly excepting prime ground, if it is
the "return" for all threat paths). Wafer probe, die
singulation and post-processing, die attach and
assembly handling all can impose threat energy that
you may not be able to anticipate in detail, to say
a particular pad gets a free pass. "Kill em all" is the
no-worries way. Anything else depends on you being
100% right about only doing "the important 90%".
Really the assembly groundrules should be provided
to you, based on the planned product manufacturing
flow and your downstream vendor lineup. If this has
not happened, it's on you to make it happen before
anyone commits much effort to layout.