Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Fixing setup and hold violations in Cadence Encounter

Status
Not open for further replies.

biju4u90

Full Member level 3
Full Member level 3
Joined
Dec 10, 2014
Messages
172
Helped
3
Reputation
6
Reaction score
3
Trophy points
18
Visit site
Activity points
1,437
Hi,
I am new to SOC Encounter and I am using First Encounter. When I try to do the physical design flow, I am having setup violations after nanorouting stage. The violation remains even after optimizing the design. I've read that addition of buffers will resolve the issue. But how can I add buffers in the design?? How can I identify where to put these buffers?
 

Well the tool will identify the buffers using function statement in the .libs. So any function A=Y will be considered as buffer. You can use eco_opt_design -hold to fix the hold times. I am assuming you will be adding parasitics and other other design rule constraints to EDI interface.
 

@artmalik: Thanks for replying. I am using Encounter 9.1 version and there is no eco_opt_design command in the tool. Actually, I am not having any hold violation, but I do have setup violations. Its seen that the setup violation gets reduced if I optimize the design again and again. After 5 or 6 optimizations, my timing reports show no violations!!.. Is this an acceptable method??
Instead of doing multiple optimizations, how can I resize the cells or add buffers in my design??

- - - Updated - - -

The timing summary is added here.

Before optimization:

+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -1.304 | -1.304 | 0.185 | -0.455 | N/A | -0.560 |
| TNS (ns):| -44.911 | -43.359 | 0.000 | -1.552 | N/A | -0.930 |
| Violating Paths:| 78 | 60 | 0 | 18 | N/A | 2 |
| All Paths:| 1087 | 476 | 559 | 57 | N/A | 24 |
+--------------------+---------+---------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.094 | 0.094 | 2.348 | 0.756 | N/A | 0.250 |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | 0.000 |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | 0 |
| All Paths:| 553 | 476 | 41 | 41 | N/A | 12 |
+--------------------+---------+---------+---------+---------+---------+---------+

After 1st optimization:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.295 | -0.295 | 0.174 | 0.002 | N/A | -0.219 |
| TNS (ns):| -1.059 | -1.059 | 0.000 | 0.000 | N/A | -0.244 |
| Violating Paths:| 9 | 9 | 0 | 0 | N/A | 2 |
| All Paths:| 1087 | 476 | 559 | 57 | N/A | 24 |
+--------------------+---------+---------+---------+---------+---------+---------+

Second optimization:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.266 | -0.266 | 0.173 | 0.058 | N/A | -0.266 |
| TNS (ns):| -0.581 | -0.581 | 0.000 | 0.000 | N/A | -0.284 |
| Violating Paths:| 8 | 8 | 0 | 0 | N/A | 2 |
| All Paths:| 1087 | 476 | 559 | 57 | N/A | 24 |
+--------------------+---------+---------+---------+---------+---------+---------+

Third optimization:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.050 | -0.050 | 0.180 | 0.060 | N/A | -0.050 |
| TNS (ns):| -0.050 | -0.050 | 0.000 | 0.000 | N/A | -0.050 |
| Violating Paths:| 1 | 1 | 0 | 0 | N/A | 1 |
| All Paths:| 1087 | 476 | 559 | 57 | N/A | 24 |
+--------------------+---------+---------+---------+---------+---------+---------+

Fourth optimization:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.125 | -0.125 | 0.179 | 0.021 | N/A | -0.125 |
| TNS (ns):| -0.130 | -0.130 | 0.000 | 0.000 | N/A | -0.125 |
| Violating Paths:| 2 | 2 | 0 | 0 | N/A | 1 |
| All Paths:| 1087 | 476 | 559 | 57 | N/A | 24 |
+--------------------+---------+---------+---------+---------+---------+---------+

After fifth optimization:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.004 | 0.004 | 0.177 | 0.044 | N/A | 0.004 |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | 0.000 |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | 0 |
| All Paths:| 1087 | 476 | 559 | 57 | N/A | 24 |
+--------------------+---------+---------+---------+---------+---------+---------+
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top