Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Fixes for Clock Gating Setup and Clock Tree Pulse Width

Status
Not open for further replies.

aditya1579

Member level 2
Member level 2
Joined
Jan 2, 2013
Messages
47
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,624
Hi,

How do we fix Clock Gating Setup violation and Clock Tree Pulse Width violation ?

Thanks,
Aditya
 

the setup time violation is fixed just like any other flop. there is nothing special about it. Clock tree pulse width violation is something which you have to check if the .lib is correct because the frequency should be low enough to handle the pulse width requirements.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top