@TrickyDicky @linam , thank you both for your input
I was on my way to draw a block diagram on how it should look when i came across this excelent link
https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/
@linam I looked at that link i did not understand why floating point numbers need to be normalized before converting to fixed point ? , also won't that affect the filter because you are now using different coefficients ?
@TrickyDicky I came across one of your older posts
https://www.edaboard.com/threads/203061/ , after looking at the fixed point library header at
https://github.com/ctn-waterloo/nef-fpga/blob/master/contrib/fixed_pkg/fixed_pkg_c.vhd , i guess what you mean is that this package is only ment to work with "VHDL-93 supported compilers "
So my question would be did you try this on ISE ( XST) or on Vivado( i guess a new synthesis engin) ?
I was also wondering how we could keep the coefficients on a FPGA , do you need to manually instantiate a BlockRAM and keep it or would it be possible to inter storage
by using VHDL , what is the best for performance , if possible an example would be great
from the following code , what does the synthesizer which supports the fixed_point package do ? , does it insert additional logic to manage the binary point ? , but the adder synthesized would be the same as the interger one right ?
Code:
signal n1,n2 : ufixed(4 downto -3);
signal n3 : ufixed(5 downto -3);
begin
n1 <= to_ufixed (5.75,n1); -- n1 = "00101110" = 5.75
n2 <= to_ufixed (6.5,n2); -- n2 = "00110100" = 6.5
n3 <= n1+n2;
Thanks in advance