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fixed point addition in verilog

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student13

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hello,

i need to implement fixed point signed addition of 16 bits at every clock edge for CORDIC algorithm. but the very first addition is overflowing, can anyone tell me how to correct overflow or the method to work with fixed point with overflow. i am using 1 sign bit, 1 integer bit, 14 fraction bits (Q2.14 format).
 

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