Yes same address for entire burst. But can data change from one beat to another
exmaple
Fixed burst
Burst lengh 2
Data bus width 32
beat 1 : ABCD
beat 2 : 120F
The address sent is the starting address, the address is auto-incremented by the slave and the data transfer beats have whatever data the master wants to send.
This is all explained in the Amba AXI spec. You might want to go download it from the ARM website.
Yes same address for entire burst. But can data change from one beat to another
exmaple
Fixed burst
Burst lengh 2
Data bus width 32
beat 1 : ABCD
beat 2 : 120F
FIXED - In a fixed burst:
• The address is the same for every transfer in the burst.
• The byte lanes that are valid are constant for all beats in the burst. However, within those byte
lanes, the actual bytes that have WSTRB asserted can differ for each beat in the burst.