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FIX Hold Violations in different Modes/Corners

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vivekgaddale

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HI,
Hold violation can be fixed by adding a delay buffer at the Flop, provided the setup violation dont occur at that flop.
So adding a buffer, should be done considering the setupmargin.

So my question is if the setupmargin doesnt match with the hold in different mode/corner for the same path/flop then how to fix?

Regards,
VivekG.
 

trav1s

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What EDA tools are you using? Or are you just asking about the general concept?
 

vivekgaddale

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Am using PT,
there is scenario, to fix hold , if the setup margin gets violated in different modes, do any one know?
 

lostinxlation

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If that happens, one of the followings applies.

1. You are inserting a buffer at the wrong location.
2. flops/latches have huge setup times and huge hold times and you should talk to whoever designed cells.
3. You are running extremely high clock frequency and adding one buffer can easily kill the setup margin.

#2 is unlikely.
If #1, find a right location to insert a buffer.
if #3, rethink your design.

I had a similar issue on Ethernet interface, where MII, RMII, SMII, SSSMII had different timing requirement. I added muxes to separate the paths for 4 modes and fix the hold in a certain mode wihtout any timing impect in other modes.

BTW, this statemetn is wrong.
Hold violation can be fixed by adding a delay buffer at the Flop
 
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