Jan 20, 2014 #1 A Anna_fpga Newbie level 1 Joined Jan 20, 2014 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 6 Hi all, I am new to verification framework development for FIRMWARE in Systemverilog . The firmware has been developed in VHDL. Does the firmware and the verification environment can be written in different languages? Does the verification framework developed in systemverilog could understand the firmware written in vhdl? Please help me Thanks Anna
Hi all, I am new to verification framework development for FIRMWARE in Systemverilog . The firmware has been developed in VHDL. Does the firmware and the verification environment can be written in different languages? Does the verification framework developed in systemverilog could understand the firmware written in vhdl? Please help me Thanks Anna