Re: Developing Comblock Platform Com-1000 with Xilinx FPGA
I explain to you my STEPS:
:arrow:I use
Filter Design Analysis FDA Matlab Toolboxes, for
.coe file creation. When i set parameters filter quantization, i can decide to specify precision, output rounding, signed or unsigned coefficient etc etc.
I choose:
- 21 taps lowpass fir filter with window kaiser beta=0.5
- fs=40 mhz,
- fpass=10mhz
- coeff width 16 bits, signed, fixed point,
- datainput 10 bits, output 10bits with rounding convergence mode
:arrow: After I use ISE 9.2i - IP CORE GENERATOR
Filter Compiler 3.2i for my
XILINX XC2S200 SPARTAN II FAMILY
insert .coe file and set coefficient parameter, but there is not a solution, in the second step, i cant't select rounding output mode!
After matlab toolboxes settings, an other time, i must select sampling frequency, clock frequency and so on... is it normal?
The information i think is in the .coe file...isn't it? Instead i must insert the same parameters in filter compiler but not output rounding mode :-(
What is a solution? Can i truncate from 31 to 10 bit?