--
entity Signal_generator is
port(clk,Go,Stop:in std_logic;
Up,Down:out std_logic);
end Signal_generator ;
---------
architecture Signal_generator of Signal_generator is
type state is (state1,state2,state3);
signal pr_state,nx_state: state;
begin
--------
process(clk,stop)
begin
if (stop='1')then
pr_state<= state1;
elsif (clk'event and clk='1') then
pr_state<=nx_state;
end if;
end process;
-------
process(Go,pr_state)
begin
case pr_state is
---1----
when state1 => if(go'event and go='1') then
up<='1' after 10 ms;