There are lot's of conditions buddy. For IO's minum size will follow 25um to 60 um width.
And for matching transistors we prefer to put square type, to match all the process gradients. For current mirrors we prefer to put in a row. Becoz those will be lot's of numer in fingers. If we try to put them in square it will occupy lot's of space.
So in general ckts, the transistor finger width will range from 4um to 10um or 12um.
Better not to put more than that.
For IO ckts (ESD), it will be range from 25um to 60um. We prefer to put larger width in IO's. Because we will be having more space to put VIA's. Inthose ckts, we generally consider current ratings, not gate resistance.
In normal ckts, currents ratings will be very less and the functionality and paracitics will try to reduce. Please correct me if I am wrong anywhere.
Now coming to your example, if you tell me the ckt which you are using I can help you to decide the finger width. Thank You.