Nov 11, 2014 #1 E electronics20 Full Member level 1 Joined Apr 27, 2011 Messages 99 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Activity points 1,888 Dear everyone I need to simulate an SRAM cell in HSPICE via FinFET technology. How do I perform this? It means, for example, in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this instruction? Many Thanks
Dear everyone I need to simulate an SRAM cell in HSPICE via FinFET technology. How do I perform this? It means, for example, in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this instruction? Many Thanks
Nov 11, 2014 #2 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,305 Trophy points 1,393 Location Germany Activity points 44,123 electronics20 said: ... in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this construction? Click to expand... Actually the same, at least for a single gate FinFET (incl. Intel's Tri-gate device). Just the physical structure is (very) different.
electronics20 said: ... in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this construction? Click to expand... Actually the same, at least for a single gate FinFET (incl. Intel's Tri-gate device). Just the physical structure is (very) different.
Nov 12, 2014 #3 E electronics20 Full Member level 1 Joined Apr 27, 2011 Messages 99 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Activity points 1,888 I appreciate your helps. Thanks