FinFET simulation in 16nm in HSPICE

[electronics20]

Dear everyone
I need to simulate an SRAM cell in HSPICE via FinFET technology. How do I perform this? It means, for example, in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this instruction?
Many Thanks

 

[erikl]

... in CMOS, we have Drain Gate Source Bulk. Now, in FinFET, how is this construction?

Actually the same, at least for a single gate FinFET (incl. Intel's Tri-gate device). Just the physical structure is (very) different.

 

[electronics20]

I appreciate your helps. Thanks