[SOLVED] FinFET circuit design for DPA

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Lijitha Vegi

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Is there a way that I can measure dynamic power variance and leakage power variance separately for a given FinFET based circuit?
 

I think you can analyze the leakage power variance (vs. voltage ?) alone if you don't clock the circuit.
 

I am not using a clock. I have a universal logic cell which I'll use in the design of combinational and sequential circuits.
 

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