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finding output resistance of FET using cadence

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BartlebyScrivener

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I have a couple of questions from a design of a current mirror I have made. The circuit is shown below

Screen Shot 2013-11-05 at 14.40.03.png

I have completed a DC sweep and a parametric analysis for values of L to get the following result

Screen Shot 2013-11-05 at 14.50.57.png

My questions are

1) I can see that channel length modulation is inversely proportional to the channel length; Is this because the change in channel length for a given change in Vds is the same irrespective of channel length, thus the ratio of (change in channel length) / (Channel Length) decreases?

2) How would I use cadence calculator to work out the output resistance, i.e how could I graph the partial derivative of Vds/Id be shown?

Thanks!

- - - Updated - - -

On pen and paper, I have worked out that the drain current is proportional to 1/L^2 so I understand the changing of CLM. But I still can't work out number 2.

Basically, I would like to use the calculator to plot values of the output resistance for a DC sweep of Vload,

where the output resistance is the derivative of Vload / Drain Current

I want to see the output resistance be very high, then reduce!

Thanks.

- - - Updated - - -

I think I got it! I clicked deriv when selecting the current to get the following.

Screen Shot 2013-11-05 at 17.12.23.png

But for some reason, this shows that the output resistance is highest for the shortest channel!? That seems wrong to me.
 

The derivative is conductance rather than resistance.

To read anything from the graph you would adjust the Y scale to show the saturated part of the characteristic with reasonable resolution.
 
Thanks for your help, schoolboy error, I did 1/deriv(I), but now I get the following.

Screen Shot 2013-11-05 at 18.21.34.png

I would have thought the resistance would be relatively constant in saturation? Have I done something wrong with the calculator?
 

For higher values of drain to source voltage You see a "2nd order effects" bounded with high value of lateral field - for 1um channel length and 1V of Vds You have 1MV/m of electric field. This causing a many effects changing your output resistance.
 

Hi,
We cant have a saturated output resistance because of the channel length modualtion effect and Leff variation..

The mirrroring is also perfect for somewhat higher Length only to avoid lonlinearity in Leff and to reduce channel length modulation...

Thanks
 

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