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# Find a minimum value and index of big array of 32 bits elements in Verilog - Help!

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#### sweetlies12

##### Newbie level 5
Hi experts,
I'm start to learn verilog and new member and I have a lot of troubles.
Could you tell me how to find a minimum value and index of big array of 32 bits elements in Verilog. How to scan all array. How should I store elements efficiently in memory, because I have to access it simultanously. I'm appreciated if anyone can give me detail example.

Thank you very much for your help.

If you need to access all elements simultaneously, you wont be storing the elements in a ram.

sweetlies12

### sweetlies12

Points: 2
If you need to access all elements simultaneously, you wont be storing the elements in a ram.

Could you give me a detail solution to my problem please, I have scan all the elements of array. I'm struggling about the solution

if you need to scan through the elements, usually you would send a count value as the address to the ram and access each value on subsequent clock cycles.

How can I store the the array if don't use ram as you said. For example I have array of N vector, each vector has 128 elements and one element is 32bits long.
Another question I need your help : if I have 2 array like that ( array A and array B ). For each one vector i of array A, find vector j of array B satisfying distance(i,j) mininum ( use Euclid distance )

Thank you for your kind help.

if you dont use a ram all values will be stored in logic. And your FPGA will fill up very very fast.

sweetlies12

### sweetlies12

Points: 2
if you dont use a ram all values will be stored in logic. And your FPGA will fill up very very fast.

Sounds like a homework problem. My mind goes blank to such problems - you'll have to help me understand it with the code you've written so far.

Thanks TrickyDicky,
please help me another question : My C code have two for loop( 1 outer , 1 inner loop ) with big number of iteration. Could you briefly tell me how to implement it in verilog. I'm very confusing.

Verilog isn't a SW language. If you can't visualize the HW circuit you are building you're never going to write working Verilog code. I'm sure your confused because you're thinking like a SW type who only knows how to write sequential code and can't think parallel implementations.

Verilog isn't a SW language. If you can't visualize the HW circuit you are building you're never going to write working Verilog code. I'm sure your confused because you're thinking like a SW type who only knows how to write sequential code and can't think parallel implementations.
Yeah,I'm newbie so I need to learn from experts here. Could u tell me how to parallel in my case. I think I can not unroll the for loop because of big iteration. Is "generate for" useful in this case ?
Also, dividing into many sub-array seem not to useful because I have to scan all elements of array.
Could u give me some solution for parallelism ?

Yeah,I'm newbie so I need to learn from experts here. Could u tell me how to parallel in my case. I think I can not unroll the for loop because of big iteration. Is "generate for" useful in this case ?

"generate for" unrolls the loop as well, rather explicitely.
Also, dividing into many sub-array seem not to useful because I have to scan all elements of array.
Could u give me some solution for parallelism ?

You haven't even defined the specs. How fast should it be, how blah blah fill in details.

Reason I mention that: if this thing is allowed to be "slow", then you can slooooowly iterate over all elements as TrickyDicky pointed out with a ram + counter. Hell, you haven't even defined how that "big array of 32 bits" is stored. One would assume this array is some sort of ram, and if it is BIG then you can store it in a block ram. If "big" is only "big" on the piece of paper called homework, but in reality is small, you can also use fpga fabric flipflops for your ram. If you should or not is another matter.

Short version: block ram + counter + iterate over all block ram entries == problem solved. And no I do not have code for that. All that seems to be in stock for today is something labeled "Specific answers to specific problems, preferably with some code".

sweetlies12

### sweetlies12

Points: 2
you can try a divide an conquer algorithm. eg, if you want to find the minimum of 6 2 7 3 8 1 9 4:
step 1: (6 > 2) (7> 3) (8> 1) (9>4)
step 2: (2 < 3) (1 < 4)
step 3: (2 > 1)
result: 1

Where it is assumed you can read/compare all values at the same time. This may not be the case if you must store the data in BRAM or distributed ram in order to fit in the FPGA.

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