heythem2008
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well... if you want - just try;heythem2008 said:but i don't use the wrfull i want just use the wrempty
and rdempty
add to your simulator 'rdclk' and 'wrclk' of the fifo and you will see whereheythem2008 said:Morover i think the problem is due to the read clock
your schematic is wrong from logical point of view, so it's not good for anyheythem2008 said:does my schematic allow me to get my purpose?
if not can you help me to obtain a good one.
it's not so important what is your data source and receiver,heythem2008 said:ok, i want use a fifo to save the samples obtained from
my 8bits adc/.../
very simple solution assuming write and read clock is the same:heythem said:/.../cut off with 128 samples my adc/.../
for the reception i need when the fifo is full to start reading
forgot it ...the problem is in the delay of receiving
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