fifo-updation of read and write ptrs

[shyamsundar]

HI EVERYBODY I M TRYING TO WRITE A CODE FOR FIFO AND GOT THIS SAMPLE FROM THE NET. NOW I HAD WRITTEN A TESTBENCH FOR THIS AND IN THE FUNCTIONAL SIMULATION I M UNABLE TO GET THE READ AND WRITE POINTERS UPDATED. CAN ANYONE HELP SOLVE THIS PROBLEM??

module fifo2(clk, rst, fr, fw, data, out);
parameter fifo_width=8, fifo_depth=16, ptr_width=4;
input clk, rst, fr, fw;
input [fifo_width-1:0]data;
output [fifo_width-1:0]out;
wire full, empty;
integer j;
reg [fifo_width-1:0]out;
reg [ptr_width-1:0]wp;
reg [ptr_width-1:0]rp;
reg [fifo_width-1:0]stack[fifo_depth-1:0];
reg [ptr_width-1:0]fifo_count;

/***********************************************
If this is a write access, put the data on the
input bus into the location pointed to by the
fifo write pointer
************************************************/
always @ (posedge clk)
begin
if (fw) begin
stack[wp] <= data;
end
end

/***********************************************
If this is a read get the data that is in
the location pointed to by the read pointer
and put it onto the output bus
************************************************/
always @ (posedge clk)
begin
if (fr) begin
out <= stack[rp];
end
end

/************************************************
Increment the write pointer on every write and
the read pointer on every read
************************************************/
always @ (posedge clk)
if (rst)
wp <= 0;
else
wp <= (fw) ? wp + 1 : wp;

always @ (posedge clk)
if (rst)
rp <= 0;
else
rp <= (fr) ? rp + 1 : rp;


/*********************************************
The fifo counter increment on every write and
decrement on every read
**********************************************/

always @ (posedge clk)
begin
if (rst) begin
fifo_count <= 0;
end
else begin
case ({fw,fr})
2'b00: fifo_count <= fifo_count;
2'b01: fifo_count <= (fifo_count == 0) ? fifo_depth:fifo_count - 1;
2'b10: fifo_count <= (fifo_count == fifo_depth) ? 0:fifo_count + 1;
2'b11: fifo_count <= fifo_count;
endcase
end
end

//assign fifo_hf = (fifo_count >= 4);
//assign fifo_he = (fifo_count <= 4);
assign empty = (fifo_count == 0);
assign full = (fifo_count >= fifo_depth);

endmodule //of fifo


//-----------------------------TEST BENCH-----------------------------------------------
module fifo_tb;
parameter fifo_width=8, fifo_depth=16, ptr_width=4;
reg clk, rst, fr, fw;
reg [fifo_width-1:0]data;
wire [fifo_width-1:0]out;
wire full, empty;
integer h;
reg [ptr_width-1:0]wp=0,mp=0;
reg [ptr_width-1:0]rp=0;
reg [fifo_width-1:0]mem[fifo_depth-1:0];
reg [ptr_width-1:0]fifo_count;
fifo2 f1(clk, rst, fr, fw, data, out);
initial
begin
clk = 1'b1;
rst = 1'b1;
$readmemb("stimuli_fifo.txt", mem);
h=$fopen("result_fifo.txt");
#20 rst = 1'b0;
end
always
#5 clk = ~clk;

initial
begin
#30 fw = 1'b1;
#30 fr = 1'b1;
#120 fw = 1'b0;
#10 fr = 1'b0;
end
always @(posedge clk)
begin
if(fw)
begin
data = mem[mp];
mp = mp+1; // INCREMENT mem INDEX
if(full)
$display(" FIFO OVERFLOW");
else if(empty)
$display("FIFO UNDERFLOW");
end
end

always @(posedge clk)
begin
$display("out = %d, data = %d", out, data);
$display("fifo_count = %d", fifo_count);
$fdisplay(h,"out = %d", out);
end
endmodule [/quote][/code]

 

[echo47]

Your testbench's full, empty, wp, rp, (and maybe some other signals) are not connected to their counterparts in fifo2. I don't know if you did that deliberately for some reason.

In module fifo2, wp and rp change from zero to 'x' soon after reset, because fr and fw are 'x' at the beginning of simulation. Try initializing fr and fw to zero in your testbench.

I don't see any data activity. Could be another problem.

Happy Verilogging