FIFO-SRAM Interfacing

[Sugam]

I have designed an asynchronous FIFO and SRAM in VHDL using asynchronous handshaking protocols They individually work fine but when I try to interface them with each other, I am not able to get the desired output. Can anyone please tell me the probable mistakes I may be making?

 

[TrickyDicky]

You dont provide much detail.

Is the FPGA side fully asynchronous? you run all sorts of timing risks with this approach

 

[rberek]

Also, your vague question makes it sound like you are trying to interface two memories with each other. I would expect nothing to happen if I interfaced two memories together, as memories usually just respond to commands and do not generate any of their own.

Please give us more information.

r.b.

 

[Sugam]

Both the modules are fully asynchronous. Data (in which the control signals for SRAM specifying the addresses, chip enable pin and W/R pin are also multiplexed) and asynchronous control signals of 'request' and 'ack' are assumed to be input to the FIFO through the controller. The FIFO further propagates the data packet to SRAM if W/R pin of SRAM is high and 'Req' of SRAM is high. If W/R is low, data is output from the SRAM

 

[TrickyDicky]

Usually, you would make the FPGA fully synchronous to make your life easier.