No it doesn't.
It comes down to what must not happen and what is acceptible to happen.
What is reported to write clk domain is full signal which is synchronized to write clk. What must not happen to write clk domain is FIFO not reporting the full condition when it becomes full. What is acceptible to happen is FIFO reporting full condition when it's not full.
Since full signal is synchronized to write porinter, it immediately reports the full condition as soon as it happens, so that it will never miss or delay the reporting of full condition therefore buffer overrun never happens. In the meantime, read pointer keeps counting up and making more room in FIFO, but it may not be reflected to full signal due to slower write clk. That is acceptible to happen since it is reporting full condition while FIFO is not full, and it doesn't hurt the functionality of FIFO. Just hits some performance.
The same also applies to empty signal in read clk domain. I wouldn't explain it and you can think how it works by yourself, but the idea is the same as full condition.