Apr 16, 2009 #1 O ombadei Member level 3 Joined Sep 1, 2008 Messages 62 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,754 fifo examples Hi, Is there any examples in VHDL to use the FIFO generator Xilinx IP CORE? Thanks
Apr 18, 2009 #2 O ombadei Member level 3 Joined Sep 1, 2008 Messages 62 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,754 xilinx fifo gemnerator example thanks for the reply.. But i would like to use the SPARTAN3's block ram.. currently.. i have created the fifo coregen.. and testing it by writing and reading it.. however, my problem rite now is reading from the fifo.. very baffling.. can't seem to detect the VALID signal in my state machine..
xilinx fifo gemnerator example thanks for the reply.. But i would like to use the SPARTAN3's block ram.. currently.. i have created the fifo coregen.. and testing it by writing and reading it.. however, my problem rite now is reading from the fifo.. very baffling.. can't seem to detect the VALID signal in my state machine..