FIFO Generator Examples

[ombadei]

fifo examples

Hi,

Is there any examples in VHDL to use the FIFO generator Xilinx IP CORE?


Thanks

 

[ombadei]

xilinx fifo gemnerator example

thanks for the reply..

But i would like to use the SPARTAN3's block ram.. currently.. i have created the fifo coregen.. and testing it by writing and reading it..

however, my problem rite now is reading from the fifo.. very baffling.. can't seem to detect the VALID signal in my state machine..