ssudhasa
Newbie level 6
fifo depth design
Hi,
I need to provide the delay of 16 clock cycle, using FIFO.
if write frequency and read frequency is same and phase is also same,
then FIFO Depth should be ?
options are :
(1) 16
(2) >16
(3) <16
Thanks for anticipation !!
Hi,
I need to provide the delay of 16 clock cycle, using FIFO.
if write frequency and read frequency is same and phase is also same,
then FIFO Depth should be ?
options are :
(1) 16
(2) >16
(3) <16
Thanks for anticipation !!