I was asked a FIFO question but to find the number of input clock cycles required and not the usual question about the depth. Please post your answers, this is not a very tough question but took me some time due to lack of practice mostly.
Given: The read cycle in a FIFO is 500MHz whereas the read cycle is 300MHz. We can fill the FIFO with a maximum of 100 entries. so the question was how many input clock cycles are required to fill the FIFO.
Assuming that I read/write at every clock edges:
I can write 500 entries and at that time 300 would be read off. This leaves a deficit of 200. (ignoring FIFO size).
So we have to write 250 entries and at that time 150 would be read off leaving deficit of 100.