FIFO circular queue buffer issue

[manasic]

hello friends;

I am implementing a circular queue fifo buffer: I am having a issue that when a simulation signal read enable is given my waves stop appearing. I think its some issue with my implementation. can anyone help: following is my FIFO code and the test bench is attached along with:

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Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
 
entity FIFO_buffer is
port ( clk: in std_logic; 
       rst : in std_logic;                                                                    -- system clock;
       re : in std_logic;                                                                     -- read enable;
       we : in std_logic;                                                                     -- write enable;
   datain : in std_logic_vector(7 downto 0);                                                  -- datainput;
   dataout : out std_logic_vector(7 downto 0);                                                -- dataoutput;
      req  : out std_logic;
      empt : inout std_logic;                                                                 -- buffer empty status;
      full : inout std_logic);                                                                -- buffer full status;
end FIFO_buffer;
 
architecture behavior of FIFO_buffer is
  
   type buffertype is array (0 to 15) of std_logic_vector(7 downto 0);                        -- buffer depth;
   signal depth: buffertype := (others => (others => '0'));                                   --contents of buffer at the time of initialisation
   signal rdptr :  unsigned(3 downto 0) := "0000";
   signal weptr :  unsigned(3 downto 0) := "0000";                                            -- read and write pointer
   constant zero : unsigned (1 downto 0):= "00";
   constant one : unsigned (1 downto 0):= "01";                                       
   begin
--________________________________________________________________________________________________________________________________________________                                                                                        
    
process(clk,rst,re,we,rdptr,weptr,full,empt)                                               -- process to write or read data and increment pointers
begin
if rst='1' then
rdptr <= (others => '0');
weptr <= (others => '0');
empt <='1';
full <='0';
end if;
  
if ((re = '1') or (full = '1')) then 
    rdptr <= rdptr + one;
    dataout <= depth(to_integer(rdptr)); 
end if;
 
if ((clk' event and clk = '1') and ((we = '1') or (empt = '1'))) then
      depth(to_integer(weptr)) <= datain;
      weptr <= weptr + one;
end if;
 
if (weptr + one = rdptr) then 
    full <='1';
else
    full <='0';
end if ;
 
if (rdptr = weptr ) then 
    empt <='1';
else
    empt <='0';
end if ; 
end process;
--____________________________________________________________________________________________________________________________________________________
requestgeneration:process(full,empt,rdptr)                                                          -- process to generate request to arbiter
begin
if ((full = '1') or (empt = '0') or (rdptr > "0010")) then
    req <= '1';
elsif ((empt = '1') or (rdptr < "0010")) then
    req <= '0';
end if;
end process;
end behavior;
 
[ /syntax ]
 
test bench:
 
[syntax=vhdl]
 
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
 
 
entity test_fifo is
end entity;
 
architecture behavior of test_fifo is
component FIFO_buffer is 
   port (
       clk : in std_logic;
       rst : in std_logic;                                                                    -- system clock;
        re : in std_logic;                                                                     -- read enable;
        we : in std_logic;                                                                     -- write enable;
    datain : in std_logic_vector(7 downto 0);                                                  -- datainput;
   dataout : out std_logic_vector(7 downto 0);                                                -- dataoutput;
      empt : inout std_logic;                                                                   -- buffer empty status;
      full : inout std_logic;
--weptr_stat : inout std_logic_vector;
--rdptr_stat : inout std_logic_vector;
      req  : out std_logic);                                                                  -- buffer full status;
end component;
 
signal clk_t : std_logic := '0';
signal rst_t : std_logic := '0';
signal re_t  : std_logic := '0';
signal we_t  : std_logic := '0';
signal datain_t : std_logic_vector(7 downto 0) := "00000000";
 
begin
  
fifo1: FIFO_buffer port map (clk_t,rst_t,re_t,we_t,datain_t);
 
inputdata:process(we_t)
          begin
          if (we_t = '1') then
              datain_t <= "00001111";
          end if;
          end process;
 
systemclock:process
            begin
            clk_t <= '1';
            wait for 1 ns;
            clk_t <= '0';
            wait for 1 ns;
        end process;
        
systemreset:process
            begin
            rst_t <= '0';
            wait for 100 ns;
            rst_t <= '1';
            wait for 1 ns;
            end process;
        
readenab:  process
          begin
            re_t <= '0';
            wait for 76 ns;
            re_t <= '1';
            wait for 76 ns;
          end process;
writeenab :  process
          begin
            we_t <= '1';
            wait for 5 ns;
            we_t <= '0';
            wait for 5 ns;
        end process;
sumulation:process
  begin
   wait for 1000 ns;
   assert false report "end simulation" severity failure;
  end process;
end behavior;
 
[ /syntax ]
 
Thanks
Manasi

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[TrickyDicky]

When re is '1', the rdptr is incremented. But the process is also sensitive to rdptr, meaning it keeps incrementing in 0 time in an infinite loop (hence why the simulation freeze).

You are not following the proper coding templates. Counters must be inside a clocked part of a process. It is also bad practice to "and" anything with a clock, it should be inside the clock if branch.
All that should be in the senstivity list for a clocked process is (clk, reset)

 

[manasic]

Thanks;

see its an evident difference between a newbie and an expert. Thanks , it helped me a lot and it worked.

Manasi