Hi, I am looking around and I found this code from VHDLguru website. I see a type which is i am not familiar with which is record. Can anyone explain to me in a simple manner about what is record in this code mean?
Second question, in this example he write sum.r, may I know what does this mean? Does it say that sum will be type r?
What I do not understand is that despite it said that it is complex in the record r and i both declared to be real?
Code VHDL - [expand]
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begin
sum.r:=n1.r + n2.r;
sum.i:=n1.i + n2.i;return sum;
Thanks a lot. And yes I am a completely newbie who wants to learn so please be patient with me. Thank you.
VHDLguru isn't really a Guru of VHDL, that is just the name of the site. Records ARE synthesizable. I'm using them in the design I'm working on right now. They were also in a design I worked on in my previous job.
sum.r refers to the sum record (the signal name that was declared as the complex record type) with the .r denoting the r part of the record.
Oops, missed that. Didn't even notice there were real types in there.
should have noticed, since I added the syntax tags to their post (never looked at their post after editing).
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Just took a look at the link in the OP first post and the first question on the blog is why it's not synthesizable and the reply by the VHDLguru blog owner was there are real types in the structure and they are not synthesizable.
OP this is why if you get code from a blog yous should read everything on that blog...including the comments section. Many times people will point out problems or explain issues with the code or the blogs advice.