Feedback in Verilog

[FLY_GUY]

In the top level of my heirachy I have an output signal "LED[7:0]".
I want to pass this into a lower level module to set a register.
I want to use the signal LED as an input in the lower level module.
The compiler throws an error and says there are too many drivers on LED.

Below is a segment of the code from the top module, and the lower level module.

module top_level_mod #(
    parameter   CLK_FREQ = 25,
    parameter   SIM_MODE = 0
)
 (
    // Main clock+reset
    //
    input   wire            HOT_CLK,   // sh 29, M9  "CPLD_CLKIN"  25MHz
    input   wire            HOT_RST_B, // sh 29, R16 "PCIE_RESET0n"
  
    // LEDs
    output  wire    [7:0]   LEDS,


    //  Mapping into heirarchy.
    //  config_FPGA config_FPGA1 (
    //      .rst_b              (HOT_RST_B),
    //      .clk                (HOT_CLK),
    //
    //      .leds            (LEDS),
  
//=========================================================   
  
module config_FPGA1 (

    input   wire            rst_b,
    input   wire            clk,

    input   wire    [7:0]   leds,

How do I change the code so the output LEDS in the top level so it works as an input in the lower module to leds?

 

[barry]

i don’t think the problem is where you’re showing it. somewhere else in your code you must have two statements driving LEDS.