satishgra
Member level 3
Hi,
I have huge verilog netlists that are borrowed from ISCAS'85 benchmarks.
I want to insert a error of 0.05 on each of the gates in the circuit and run one million simulations to see the output error probability.
Is there any tool that can do this for me ...anything from synopsys , mentor, cadence or opensource.
Any quick help would be very helpful.
Regards,
Satish
I have huge verilog netlists that are borrowed from ISCAS'85 benchmarks.
I want to insert a error of 0.05 on each of the gates in the circuit and run one million simulations to see the output error probability.
Is there any tool that can do this for me ...anything from synopsys , mentor, cadence or opensource.
Any quick help would be very helpful.
Regards,
Satish