[SOLVED] Fatal error while running top module || UVM

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ranayehya

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Hello!
I am trying to run my first UVM design using these command but I get those errors

And the commands(these commands used after compiling the design file and UVM files)
Code: 
vlog AES_MoniterAFter.sv -dpiheader dpiheader.h  add.c
vsim  -coverage -t 10ns -novopt work.AES_tb_top +UVM_TESTNAME=AES_test set NoQuitOnFinish 1
onbreak {resume}
log /* -r
run -all

Is something wrong with these commands or the UVM design has an error?
Thanks..
 
Last edited:

Do you have 
Code Verilog - [expand]
1
2
3

class AES_test extends uvm_test;
`uvm_component_utils(AES_test)
...
somewhere?
 

Yes, I have. Sir, Dave Rich.
Do you want to see the code ?
 

Is that class in your AES_MoniterAFter.sv file? If not, how do you expect vsim to find it?
 

AES_MoniterAFter.sv file's job is to import a C code and predict the output. AES_test is in top module(the interfacing module between UVVM files and verilog code). I already compiled the top module.

- - - Updated - - -

I found my problem. I declared two variables with the same name + "r" in one of them. I am sorry for my bad naming and bothering you.
 

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