libraryieee;-- line 1useieee.std_logic_1164.all;-- line 2-- line 3entity find_errors isport(-- line 4
a:instd_logic_vector(0to3);-- line 5
b:outstd_logic_vector(3to0);-- line 6
c:instd_logic_vector(5downto0));-- line 7end find_errors;-- line 8-- line 9architecture not_good of find_errors is-- line 10begin-- line 11
my_label:process-- line 12begin-- line 13if(c =("00"& x"F"))then-- line 14
b <= a;-- line 15else-- line 16
b <="0101";-- line 17endif;-- line 18endprocess;-- line 19end not_good;
The error is because your process has no sensitivity list or wait statement. This means it loops forever and probably hits the simulator iteration limit. you need to put C and A in the process sentivity list:
Code VHDL - [expand]
1
my_label :process(a,c)
FvM said:
Signals a and b are not assignment compatible, different index direction.
This is not a syntax or runtime error. Assigning arrays with opposite directions of the same size is perfectly fine, though it can often be a user error. Assignments will always assign 'left to 'right, so in the OPs case, b(3) = a(0) etc.