Kgonz
Newbie level 5
Hi im pretty knew to VHDL and im trying to simulate the code that i wrote for an SPI master but when i go to wave simulations in model sim the most important waveforms dont show up MOSI, MISO, and SS. the only reason that i see that they might not be appearing is because i receive a fatal error warning
however im not sure what issue its having with line 58
Ive attached a copy of my code and the TB
Code for SPI Master
SPI Master TB
however im not sure what issue its having with line 58
Ive attached a copy of my code and the TB
Code for SPI Master
Code:
library ieee;
use ieee.std_logic_1164.all;
entity fsm_spi is
port( clk, rst, rd_enable, miso: in std_logic;
mosi, ss, sclk: out std_logic );
end entity;
architecture logic_flow of fsm_spi is
type state is (st_idle, st0_txRead, st1_txAddress,
st2_rxData);
signal present_state, next_state: state;
signal data_read: std_logic_vector(7 downto 0) ;
constant read1 : std_logic_vector(7 downto 0) :="11101100";
constant address: std_logic_vector(23 downto 0) :="110101101101011011010110";
constant max_length: natural:=24;
signal data_index: natural range 0 to max_length -1;
signal timer: natural range 0 to max_length-1;
begin
process(clk, rst)
begin
if (rst='1') then
present_state<= st_idle;
data_index <= 0;
elsif (clk'event and clk='0') then
if(data_index=timer-1) then
present_state<=next_state;
data_index <=0;
else
data_index <= data_index +1;
end if;
end if;
end process;
process(present_state, rd_enable, data_index)
begin
case present_state is
when st_idle =>
ss<='1';
sclk<='0';
mosi<='X';
timer<=1;
if(rd_enable ='1') then
next_state<= st0_txRead;
else
next_state<= st_idle;
end if;
when st0_txRead =>
ss<='0';
sclk<=clk;
timer<=8;
mosi<= read1(7- data_index);
next_state<= st1_txAddress;
when st1_txAddress =>
ss<='0';
sclk<=clk;
timer<=24;
mosi<= address(23- data_index);
next_state<= st2_rxData;
when st2_rxData =>
ss<='0';
sclk<=clk;
timer<=8;
data_read(7- data_index) <= miso;
next_state<= st_idle;
end case;
end process;
end logic_flow;SPI Master TB
Code:
library IEEE;
use IEEE.Std_logic_1164.all;
entity fsm_spi_tb is
end fsm_spi_tb;
architecture bench of fsm_spi_tb is
component fsm_spi
port(clk, rst, rd_enable,miso: in std_logic;
mosi, ss, sclk : out std_logic );
end component;
signal clk, rst, rd_enable: std_logic;
signal mosi, ss, sclk,miso: std_logic ;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin
pm : entity work.fsm_spi
port map (clk => clk,
rst => rst,
rd_enable => rd_enable,
mosi => mosi,
ss => ss,
sclk => sclk,
miso => miso);
process -- stimulus
begin
rst<='1';
wait for clock_period;
rst<='0';
rd_enable<='1';
wait for clock_period;
wait for clock_period*32;
rd_enable<='0';
stop_the_clock<=true;
wait;
end process;
process -- clock generation
begin
while not stop_the_clock loop
clk <= '0';
wait for clock_period / 2;
clk <= '1';
wait for clock_period / 2;
end loop;
wait;
end process;
end;
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