Any idea about PLL full chip level simulation?
It takes very long time to lock but i need to run simulation until PLL lock.
Do you know any fastest eda software?
yeah ,
u can use a beavioral models for the divider to speed up the simulation , i have seen the ADMS simulator of mentor , reduce the time of the PLL simulation very mch by using verilog model of the divider
If PFD and charge pump can opreate reliably at 100 times Fref. Change reference frequency to 100 times and scaling feedback divider ratio and filter capacitor to 1/100.
Use HSIM. Define all digital circuits as digital and define analog circuits such as loop filter as analog, then it will be at least 100 times faster than spice simulation.