[SOLVED] fanout problem while compiling vhdl code in libera software

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Nithyaselvaraj

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Hi,
I have declared 4 input port and 1 output port, after compilation in my compile report it is taking only that output port. not at all taking my input ports.
can anyone help me to solve



Thanks.
 

No one here the super natural power to remotely know your VHDL code and come up with an answer.
You need to post your code (*follow the rules for posting the code*) + the test bench + the compilation report in order for people to help you.
 

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