false path and multi cycle path example codes

[u24c02]

Hi.

I'm trying to implement including false path and multi cycle path RTL code for test design compiler.
So does anyone know where some example codes are ?

 

[dpaul]

http://www.sunburst-design.com/ has good papers on multi-cycle paths.
Moreover Synopsys documentation is also a good source to learn about multi-cycle paths.

"So does anyone know where some example codes are ?" - shouldn't that be specific to your design? I would learn the concept and then try to implement as per use case.

 

[u24c02]

http://www.sunburst-design.com/ has good papers on multi-cycle paths.
Moreover Synopsys documentation is also a good source to learn about multi-cycle paths.

"So does anyone know where some example codes are ?" - shouldn't that be specific to your design? I would learn the concept and then try to implement as per use case.

Thanks Sir,
I just have a query bout as following sentence.

"So does anyone know where some example codes are ?" - shouldn't that be specific to your design? I would learn the concept and then try to implement as per use case.

I don't know why you do this. Did you just rephrase from original question?

 

[ads-ee]

Multi-cycle path:

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`timescale 1ps/1ps
module mc_test;
 
  reg       clk;
  reg       rst;
 
  initial begin
    clk = 0;
    forever #5000 clk = ~clk;
  end
  initial begin
    rst = 1;
    #20000;
    rst = 0;
  end
 
  reg [1:0] cntr;
  reg [8:1] lfsr;
  reg [3:0] ff_1 = 0, ff_2 = 0;
 
  always @ (posedge clk) begin
    if (rst) begin
      cntr <= 0;
    end else begin
      cntr <= cntr +1;
    end
 
    if (rst) begin
      lfsr <= 1;
    end else begin
      lfsr <= {lfsr[1], lfsr[8], lfsr[7]^lfsr[1], lfsr[6]^lfsr[1], lfsr[5]^lfsr[1], lfsr[4:2]};
    end
 
    $display ("%t - lfsr: %h, ff_1: %h, ff_2 %h", $time, lfsr, ff_1, ff_2);
  end
 
  // multicycle registers
  always @ (posedge clk) begin
    if (cntr == 2'd3) begin
      ff_1 <= lfsr[4:1];
      ff_2 <= ff_1;
    end
  end
 
endmodule

---

Observe the display output and see that both ff_1 and ff_2 only update every four clock cycles. Even though lfsr updates every clock cycle the value loaded into ff_1 only updates every four clocks and the transfer between ff_1 and ff_2 only updates every four clocks. Both ff_1 and ff_2 have a multi-cycle path of 4.

 

[u24c02]

Thanks Sir, you always surprise me.

 

[yanshangzhao]

I think the logic that use ff_1 or ff_2 have a multi-cycle path. Because ff_1 and ff_2 's feed in logic change every cycle.