failed with iteration exhausted

[electronics20]

Hi all
I am designing an SRAM array via HSPICE 2012 in 16nm technology, but the following problem encountered me. I would be grateful if you can help me:

dcop: begin pseudo transient

dcop: ... failed with iteration exhausted

dcop: end pseudo transient


Thanks,
Regards

 

[BradtheRad]

The simulator needs to calculate several iterations of circuit action, until it reaches stable results (convergence). Then it displays the results. It goes on to a new frame.

There is a maximum limit to the number of iterations it is set to execute per frame. If it cannot reach convergence after that many iterations, it generates an error.

"Failed with iteration exhausted"... suggests your circuit is very complex. Or, perhaps you have components interacting in an unstable fashion.

You might get success by changing the timestep. Simplify the circuit if possible. Set initial parameters to reasonable expected values.

 

[dick_freebird]

Looks like this is maybe the approach where supplies
are all co-ramped from 0 to final. We used to do this
explicitly (tstore / restore) on tough circuits. But a
digital circuit with a lot of possible (and bistable) states
is not going to respond well at the point where CMOS
just starts to wake up. Too many decisions to make.

Simulating the whole array would be a tactical mistake.
Better to simulate a minimum useful block, and replicate
the rest by controlled sources (for power drain & signal
loading). Get the node and device count down while
keeping what you care about enough, to measure (by
proxy if it helps solution).

See what control you have over ITLx iteration limits,
timestep vs ramp granularity, methods (TRAP is very
likely to either numerically oscillate or fail; can you
pick Euler or Gear methods for this "special mode"?
But I think the problem is just too much simultaneous
waking-up at some ramp-point, with nothing to make
a decision.

Might try some trickery like deliberately offsetting the
cell so it always comes up "0" on supply ramp - make
the Ws a little mismatched, add a bogus high value shunt
resistor to one side of the cross coupled pair, etc.

Unfortunately analog simulators deal rather ineffectively
with "X"....

 

[electronics20]

I applied some changes such as setting initial values and reducing step time, yet my simulation does not converge.

 

[BradtheRad]

How many SRAM units are in your schematic? It may help if you trim it down to a smaller number (as suggested in post #3.)

You can try a minimal amount such as 4 or 8. Run test simulations to see if it will complete without giving an error.

16nm technology

Is it possible it will work more easily if you were to change the size? Perhaps to a larger size?

 

[electronics20]

How many SRAM units are in your schematic? It may help if you trim it down to a smaller number (as suggested in post #3.)
You can try a minimal amount such as 4 or 8. Run test simulations to see if it will complete without giving an error.
Is it possible it will work more easily if you were to change the size? Perhaps to a larger size?

512 cells are in my schematic in addition to peripheral circuits such as 6*64 decoder. I need to report 64bit SRAM array results but smaller one does not suffice this project.
Do you mean that I change the size of transistor widths or that of array?
thanks a lot

 

[BradtheRad]

512 devices sounds like a lot for a simulator to juggle.

From what I understand, SRAM is made from flip flops. They have four possible input combinations. One of them is disallowed. Were you able to ensure that no disallowed states occur in your array?

I think it will help if you were to start with a smaller array. Once you are able to get that working properly in the simulator, then add more devices.

Sorry, I'm not knowledgeable about what a simulator does about nm fabrication values.

 

[electronics20]

512 devices sounds like a lot for a simulator to juggle.

From what I understand, SRAM is made from flip flops. They have four possible input combinations. One of them is disallowed. Were you able to ensure that no disallowed states occur in your array?

I think it will help if you were to start with a smaller array. Once you are able to get that working properly in the simulator, then add more devices.

Sorry, I'm not knowledgeable about what a simulator does about nm fabrication values.

Thanks. Notably, I did these simulations based on 16nm Finfet technology, and acquiring reasonable results. However, applying CNT technology to sram array in HSPICE 2012, HSPICE simulator gives the convergence error.