I am trying to simulate the effect of bulk voltage on drain current. This question is also present in the book "Design of Analog CMOS Integrated Circuits" by Behzad Razavi. I am trying to plot the drain current as a bulk voltage varies from 0 to 3V. (please see the image attached with this thread)
I used the following spice code:
Code:
*2.5(e) of Design of Analog CMOS Integrated Circuits
V1 1 0 DC 1.5V
M1 1 2 3 4 NMOD1
VG 2 0 DC 1.9V
VS 3 0 dc 1V
VX 4 0 DC 1.5V
.MODEL NMOD1 NMOS (LEVEL=1 VTO=0.7 W=50U L=0.5U GAMMA=0.45 PHI=0.9 NSUB=9.0E+14 LD=0.08e-06 UO=350
+ LAMBDA=0.1 TOX=9.0e-9 PB=0.9 CJ=0.56E-3 CJSW=0.35e-11
+ MJ=0.45 MJSW=0.2 CGDO=0.4E-9 JS=1.0E-8)
.DC VX 0 3 0.01
.PROBE ID(M1)
.end
The simulation output file shows the following errors
"These supply currents failed to converge:
You are applying positive bulk-source and bulk-drain voltages, resulting in unlimited substrate diode currents. Despite of the question if this is a reasonable setup, you should at least connect as series resistor to the bulk terminal.