Instead of `include "math.v" in the code, i just paste the contents of math.v in the bottom side of the verilog module. So, now in case verilog also it is not showing error, but,in the vivado simulator showing output as XX. In the variance.v module instead of
function reg [`MAXIMUM_FUNC_WIDTH-1:0] pow(input integer base, input integer index);, i have written function [`MAXIMUM_FUNC_WIDTH-1:0] pow(input integer base, input integer index);. means removed reg. because it was showing error like can not set both range and type on function. But at the end output is XX please help me to solve the problem.