Facing some error in Verilog HDL coding of Standard deviation calculation?

D

Guest
The standard deviation (SD, also represented by the lower case Greek letter sigma σ for the population standard deviation or the Latin letter s for the sample standard deviation) is a measure that is used to quantify the amount of variation or dispersion of a set of data values. A low standard deviation indicates that the data points tend to be close to the mean (also called the expected value) of the set, while a high standard deviation indicates that the data points are spread out over a wider range of values.

I have a code for calculating standard deviation, everything in the codes looks ok, but when I am running the code I am getting some errors, I am using vivado 2017.4 for verilog HDL coding. The screen shot of the error and code.rar is attatched. please help me to solve the problem.

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Super Moderator
Staff member
Did you look at the xvlog.log file that the error suggests you look at?

It seems to indicate you've written your code incorrectly.

My guess would be you tried to write a software like implementation in Verilog.

wahab.khan

Newbie level 4
Also, the zip file you've attached doesn't contain source files. They seem to be located outside the vivado project folder.

D

Guest
Thank you ads-ee for the reply, I am getting some errors like
1) cannot set both range and type on function declaration
2) root scope declaration is not allowed in verilog 95/2K mode
I dont know how solve these kinds of errors.

INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/fifo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/sqrt.v" into library xil_defaultlib
ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/math.v:6]
ERROR: [VRFC 10-465] cannot set both range and type on function declaration [C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/math.v:14]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/math.v:14]
INFO: [VRFC 10-311] analyzing module sqrt
ERROR: [VRFC 10-1775] range must be bounded by constant expressions [C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/sqrt.v:66]
ERROR: [VRFC 10-1040] module sqrt ignored due to previous errors [C:/Users/KK-HP/Desktop/emd_model_journal_final/stan_devi/sqrt.v:10]

Super Moderator
Staff member
Yes, I saw those errors, but can't comment on them as post #3 noted the source is outside the project.

Look at your source and see why the things like the range are not constant.

Like I said you can't treat Verilog as if it is C even though the syntax looks similar. Verilog describes hardware and hardware can't change during run time, that would be like taking a circuit board and swapping parts in and out and rewiring it while it's running.

If you decide you can post the code for sqrt.v and math.v then you need to understand you can't later request it be deleted from the forum moderators won't accept requests to delete later, but don't expect any useful help without the code.

vGoodtimes

looks like you have clog/pow declared in a header which is included before the module. Verilog doesn't allow this and the functions are ignored. Using these incorrectly declared functions in a range also generates an error.

(SystemVerilog allows what you want. IIRC, Verilog has an interesting way of resolving functions and the error you hit is a byproduct)

D

Guest
Thank you, everyone. Although, I have copied the data from the .v, verilog to .sv system verilog file and converted the design to system verilog based design. program run with XX as the output in the vivado simulator. means not getting the desired output.
** If I mix verilog and system verilog design sources will it work (extra question).

dpaul

All Verilog constructs should work within a file marked .sv. But the opposite is not true.

D

Instead of include "math.v" in the code, i just paste the contents of math.v in the bottom side of the verilog module. So, now in case verilog also it is not showing error, but,in the vivado simulator showing output as XX. In the variance.v module instead of