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[ARM] Facing Problem to toggle GPIO Pin in LPC2103

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KVSN91

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facing a problem to toogle my portpin in lpc2103.

i wrote my code like this

Code:
#define D4  (1<<19)

while(1)
{
IOSET = D4;
Delay();
IoCLR = D4;
}
 
Last edited by a moderator:

Without knowing the details of the system oscillator configuration, one possible issue is that you have not set the I/O pin direction, which by default are configured as inputs. You will also need to insert a delay() after clearing the bit, or it will be immediately set during the next while loop iteration:

Code:
#define D4  (1<<19)

IODIR |= D4;

while(1)
{
IOSET = D4;
Delay();
IOCLR = D4;
Delay();
}

BigDog
 

I Write Like this

Code:
PINSEL1 = 0xFFFFC000; // D1,D2,D3,D4,D5,D6   
IODIR    = 0x003F000;

   while(1)
    {
      IOSET = (1<<19);
      Delay();
      IOCLR = (1<<19);
       Delay();
     }
I Take P0.19 To TOOGLE . It can't Toogle for Above CODE
 

I've seen problems related to this so I mention it just in case

There is a System Control and Status flags register (SCS - 0xE01F C1A0) and bit 0 controls if the port pins are accesed by the APB addresses or via addresses in the on-chip memory range.
If the GPIO0M bit is set to 1 then the port is controlled by FIODIR, FIOPIN, FIOSET, FIOCLR etc and IODIR, IOPIN, IOSET, IOCLR don't affect the pin state.
It's the opposite when the GPIO0M bit is set to 0, the post is controlled by IOPIN etc and not FIOPIN etc

- - - Updated - - -

Is the delay long enough? Maybe the port blinks but it's too fast to notice.
 

Hi
I Wrote SCS(GPIO0M) to '0'. but no toogling.
 

TOOGLING GPIO Port pin In LPC2103

Facing A Problem To TOOGLE GPIO Port PINS P0.19 & P0.18


I Wrote My CODE like this

Code C - [expand]
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SCS  |=(0<<0);       // GPIO VIA APB address
PINSEL1 = 0xFFFFF000 | 0x00;
                                   //D1,D2,D3,D4,D5,D6
IODIR = 0x003F0000;
 
main
{
  WDFEED = 0xAA;// Watch dog feed
  WDFEED = 0x55;
  
 
 
 
 
  While(1)
  {
     IOSET |= (1<<18);
     Delay(150);
     IOCLR |= (1<<18);
 
   }
}



Here I wnat to toogle the port pin P0.18 its not toogle. I Can,t fine what the problem is
 
Last edited by a moderator:

Re: TOOGLING GPIO Port pin In LPC2103

I'm no expert in ARM coding but it looks like it should work. P0.18 will only go low for a few cycles before returning high though. If you want it it toggle equal high and low you need an extra delay after the IOCLR instruction, at the moment it immediately follows it with the IOSET instruction in the 'while' loop.

Brian.
 

Re: TOOGLING GPIO Port pin In LPC2103

hiii
I Am Hardly try to toogle GPIO Port pins in LPC2103, But I Can't do it ,
Any code TO TOOGLE GPIO Port Pins
 

Re: TOOGLING GPIO Port pin In LPC2103

Show your circuit. There are 4 pins that has to be connected to 3.3V and 4 pins to GND. Are you using 12 MHz crystal ? What Compiler are you using ? Keil MDK ARM ?

I just finished installing MDK ARM. Tell me what package(s) I have to install from here

https://www.keil.com/dd2/pack/

to get LPC2103 device in Keil uVision. I will try to help you.
 
Last edited:

I Am Hardly try to toogle GPIO Port pins in LPC2103, But I Can't do it ,
Any code TO TOOGLE GPIO Port Pins
Did you try what I suggested?

Change the 'while()' loop to:
Code:
While(1)
  {
     IOSET |= (1<<18);
     Delay(150);
     IOCLR |= (1<<18);
     Delay(150);
   }

Tell us what happens.

Brian.
 

hi, here i am sending circuit diagram. i am using 24.5 MHz.
as per schematic we design for 12Mhz, but we used 24.5MHz crystal.
where there is a maximum limit of 25Mhz is given in datasheet. so i used 24.5Mhz.
i am using IAR embedded workbench.(IAR compiler)
lpc2103SCH1.JPG
 

finally i found my problem my pll is not working for oscillator frequency

Code:
void Oscillator_Frequency()
{      
        PLLCON       =  0x00;
        PLLFEED      = 0xAA;		// Feed Sequence
	PLLFEED      = 0x55;
        PLLCFG       = 0x22;    	//M=2,P=2
        PLLFEED      = 0xAA;		// Feed Sequence
	PLLFEED      = 0x55;
	PLLCON       = 0x01;		// Enable PLL
	PLLFEED      = 0xAA;		// Feed Sequence
	PLLFEED      = 0x55;       
	while(!(PLLSTAT & 0x0400));	// Is PLL Locked       
	PLLCON       = 0x03;		//Connect PLL After
	PLLFEED      = 0xAA;		//Feed Sequence
	PLLFEED      = 0x55;
	//APBDIV       = 0x02;		// Peripheral clock 1/2
        
}

inthis its stoped at while condition PLLSTAT is not locked
send me wirking code
 

If the PLL won't lock it is a hardware problem. If you are using 24MHz external clock and the PLL is enabled, are you exceeding the 70MHz maximum PLL speed? If you multiply by more than 2 it may not lock (3 x 24 = 72MHz!). I do not have the data sheet with me to check the multiplier value you used.

What are you expecting to happen on the GPIO pin anyway. It should toggle, high for ~150mS then low for a few uS, is that what you want it to do? You need a fairly fast oscilloscope or logic analyzer to see it change state.

Brian.
 

I am changing 24Mhz to 20Mhz crystal.but its same no work

- - - Updated - - -

is there any problem with PIns DBGSCL and RTCK,
As per my schemantic both pins are float no connectins.actually as per User Manual of LPC2103 to operate r Enable in DEBUG mode saying the DBGSEL pin to external pulled

Here i can't undersatand difference between normal operation & DEBUG mode.

is it necessary to connect RTCK pin to JTAG port pins..?

As per my schemantic i am useing for JTAG - TRST,TDI,TMS,TCK & TDO
 

I am Strucked IN this stage in my project, so i can't move another steps like uart ,i2c,spi functions

My crystal oscillator i am using 20Mhz ,(but in Schemantic 12Mhz).I want to run my program Only download without DEBUG ,

you send a program with all initialaizatins and to toogle my Portpins.

and also send me files target.h, IRQ.h,Type.h headerfiles all for LPC2103,

lpc2103SCH1.JPG
 

I ask yet again:

1. How do you know the port pin is not toggling?

2.What do you have connected to the pin to tell you if it is high or low logic state?

The schematic is good, but telling us it doesn't work isn't helping us diagnose the exact problem.
Please just answer the questions above.

Brian.
 

HI almost MY program is correct ,
i think it is may be a Debug problem
i wrote simple stratup code to my project.but it does not work. When I debug the program,hang at in PLL what for lock loop in startup code.

my code like this



Code:
void SYS_INIT()

{

PLLCFG =0X02; 

PLLCON=0X01;     //enable pll

PLLFEED=0xAA;   // feed sequence

PLLFEED=0x55;

while(!(PLLSTAT & 0x0400));  // wait for is PLL is locked

PLLCON=0x03;

PLLFEED=0xAA;

PLLFEED=0x55;

APBDIV=0x01;

}


when i am debug my code its hanged at while loop ie.. PlOCK.
in Datasheet

DBGSEL Input Debug Select. When LOW at Reset, the P0.27 - P0.31 pins are
configured for alternate use via the Pin Connect Block. When HIGH at
Reset, the debug mode is entered.

RTCK Output Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)". Also used during entry into debug mode.


i have doubt only these to pins and JTAG connector
AS per my Schmantic The DBGSEL & RTCK pins are floated ...
I saw ex reference schmantics LPC2103, mostly DBGSEL pin is connected to 3.3

- - - Updated - - -

HI almost MY program is correct ,
i think it is may be a Debug problem
i wrote simple stratup code to my project.but it does not work. When I debug the program,hang at in PLL what for lock loop in startup code.

my code like this



Code:
void SYS_INIT()

{

PLLCFG =0X02; 

PLLCON=0X01;     //enable pll

PLLFEED=0xAA;   // feed sequence

PLLFEED=0x55;

while(!(PLLSTAT & 0x0400));  // wait for is PLL is locked

PLLCON=0x03;

PLLFEED=0xAA;

PLLFEED=0x55;

APBDIV=0x01;

}


when i am debug my code its hanged at while loop ie.. PlOCK.
in Datasheet

DBGSEL Input Debug Select. When LOW at Reset, the P0.27 - P0.31 pins are
configured for alternate use via the Pin Connect Block. When HIGH at
Reset, the debug mode is entered.

RTCK Output Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)". Also used during entry into debug mode.


i have doubt only these to pins and JTAG connector
AS per my Schmantic The DBGSEL & RTCK pins are floated ...
I saw ex reference schmantics LPC2103, mostly DBGSEL pin is connected to 3.3 lpc2103SCH1.JPG
 

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