#define D4 (1<<19)
while(1)
{
IOSET = D4;
Delay();
IoCLR = D4;
}
#define D4 (1<<19)
IODIR |= D4;
while(1)
{
IOSET = D4;
Delay();
IOCLR = D4;
Delay();
}
PINSEL1 = 0xFFFFC000; // D1,D2,D3,D4,D5,D6
IODIR = 0x003F000;
while(1)
{
IOSET = (1<<19);
Delay();
IOCLR = (1<<19);
Delay();
}
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SCS |=(0<<0); // GPIO VIA APB address PINSEL1 = 0xFFFFF000 | 0x00; //D1,D2,D3,D4,D5,D6 IODIR = 0x003F0000; main { WDFEED = 0xAA;// Watch dog feed WDFEED = 0x55; While(1) { IOSET |= (1<<18); Delay(150); IOCLR |= (1<<18); } }
Did you try what I suggested?I Am Hardly try to toogle GPIO Port pins in LPC2103, But I Can't do it ,
Any code TO TOOGLE GPIO Port Pins
While(1)
{
IOSET |= (1<<18);
Delay(150);
IOCLR |= (1<<18);
Delay(150);
}
void Oscillator_Frequency()
{
PLLCON = 0x00;
PLLFEED = 0xAA; // Feed Sequence
PLLFEED = 0x55;
PLLCFG = 0x22; //M=2,P=2
PLLFEED = 0xAA; // Feed Sequence
PLLFEED = 0x55;
PLLCON = 0x01; // Enable PLL
PLLFEED = 0xAA; // Feed Sequence
PLLFEED = 0x55;
while(!(PLLSTAT & 0x0400)); // Is PLL Locked
PLLCON = 0x03; //Connect PLL After
PLLFEED = 0xAA; //Feed Sequence
PLLFEED = 0x55;
//APBDIV = 0x02; // Peripheral clock 1/2
}
void SYS_INIT()
{
PLLCFG =0X02;
PLLCON=0X01; //enable pll
PLLFEED=0xAA; // feed sequence
PLLFEED=0x55;
while(!(PLLSTAT & 0x0400)); // wait for is PLL is locked
PLLCON=0x03;
PLLFEED=0xAA;
PLLFEED=0x55;
APBDIV=0x01;
}
DBGSEL Input Debug Select. When LOW at Reset, the P0.27 - P0.31 pins are
configured for alternate use via the Pin Connect Block. When HIGH at
Reset, the debug mode is entered.
RTCK Output Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)". Also used during entry into debug mode.
void SYS_INIT()
{
PLLCFG =0X02;
PLLCON=0X01; //enable pll
PLLFEED=0xAA; // feed sequence
PLLFEED=0x55;
while(!(PLLSTAT & 0x0400)); // wait for is PLL is locked
PLLCON=0x03;
PLLFEED=0xAA;
PLLFEED=0x55;
APBDIV=0x01;
}
DBGSEL Input Debug Select. When LOW at Reset, the P0.27 - P0.31 pins are
configured for alternate use via the Pin Connect Block. When HIGH at
Reset, the debug mode is entered.
RTCK Output Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)". Also used during entry into debug mode.
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