Extractint timing and area informations from FPGA design

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lahrach

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Hi friends,

How can I extract timing and area information, using ISE 11.4 and Virtex-5

best regards
 

You can use the timing report in project navigator. There's planahead for timing analysis + floorplanning. And you can always look at what goes where in either planahead or fpga editor...
 
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